- All parts changed to 74HC high speed CMOS, no more worries about fanout limits and sinking vs. sourcing differences in current. However the unused gates (not shown) will have to be properly terminated as per the usual issues with floating hi-impedance inputs.
- Some newer parts have been used (4-bit counter, octal 3-state buffer) to simplify the design and reduces the chip count.
- The 74LS189 RAM has been replaced with a 32kB CMOS Asynchronous Static RAM. A part like the Cypress Semiconductor CY7C199CN can be used for the RAM (Digikey Part Page).
- Since the RAM uses the same pins for input and output, another set of 3-state buffers is used to output or isolate the data switches from the W-bus.
- To clean up the schematic the W-bus is only shown as a connection to a common bus.
- A logic analyzer has been added to show how the control signals are sequenced.
Here is the memory contents of a sample program entered into the SAP-1. It can be found on page 146 of Digital Computer Electronics (Example 10-3).
Link to schematic file.
Link to PDF of schematic.