The OPCode half of the instruction register outputs directly to the address lines of the micro-code ROMs. To simplify things, each instruction's microcode takes up a fixed block of 8-bytes, this allows for up to 8 micro-instructions for each routine. Each instruction has 4-bits for the OPCode so there can be up to 16 OPCodes; this iteration of the SAP-1 has 8 instructions in its set. Each machine cycle executes as follows:
- T1: Load the memory address register from the program counter.
- T2: Increment the program counter, load instruction from the RAM.
- As soon as the instruction is loaded from RAM, the ROM address now points to the microcode for that instruction.
- T3,T... Continue executing the instruction.
- NOP: This resets the Controller/Sequencer counter back to zero and the machine cycle repeats.
The contents of memory once the auto-loader has completed.
And here the contents of the accumulator has been transferred to RAM by the store instruction.
The ROM allows for much more flexibility in creating and editing the instruction set. The Jump, Store and Output memory instructions have been added to the original set.
The microcode for each instruction. Thank-you to Kyle at 8-bit Spaghetti where I first saw this nice layout for the microcode. He also has a build log of his own SAP-1 computer.
Link to a RAR file of the schematics, ROM binaries and microcode.