Here is what I call the ASAP-2 Almost Simple As Possible Computer. It is based on the SAP-2 as described in Digital Computer Electronics by Albert Malvino. I made a few changes to the design: there is only one input register, the memory is split in to a 32kB ROM and 32kB RAM, the ALU supports a Carry flag, the OPcodes no longer follow the 8085 numbering and I have more than doubled the number of OPcodes.
The basic architecture of the circuit:
Having the ALU A input directly connected to the W-bus adds a lot of flexibility to the design. I originally had a temporary register on both ALU inputs but this required another 3-state buffer on the ALU output.
The schematic was made using Proteus Design Suite version 8.0 SP1 and the demo version should be able to view and simulate the circuit.
I consider this to be a work in progress. I plan to add some more decoding on the controller/sequencer to get the number of ROMs down to 4 (ROMs $ > 74HC138 $). It was probably a mistake to change the I/O functions to 1 byte commands as this limits the ability to address and expand the I/O bus. Also, adding some OPCodes that use the B/C registers as a memory address pointer would be useful.