Saturday, May 4, 2013

SAP-1 Simple as Possible Computer with Discrete Component RAM

I have been asked a few times how to design a 16-byte RAM using standard TTL parts.  One way to do this is to use 8-bit registers to hold each byte.  A 74LS373 is an 8-bit latch type register with 3-state outputs, several chips can share the same input and output buses.  Two 74LS138 and two 74HCT238 3-bit to 8-line decoders are used for decoding the addresses.

Each decoder has two active low enable inputs and one active high enable input.  Internally they translate a 3-bit number to activate 1 out of 8 outputs.  The '138 has active low outputs, if the chip is not enabled then all outputs are high.  The '238 has active high outputs, if the chip is not enabled then all outputs are low.  The least significant 3 bits of the 4-bit address (from the MAR) connect to the select inputs.  The most significant bit connects to the (active low) enable of the first decoder and the (active high) enable of the second encoder.  So addresses 0 through 7 activate the lowest 8 lines and addresses 8 thought 15 activate the highest 8 lines.  Finally, either the WEram (write enable ram) or CE (chip enable) signals must go low for any of the control signals to activate.

These Input and Output signals go to each individual register chip.  To enter data, the address and data is set using the DIP switches (in Program mode) and the Write Memory button is pressed.  This sets the LE signal of the register high and the data is latched in to memory.  When reading data the controller/sequencer sends the CE signal to the memory decoder and whichever register is selected by the MAR outputs its data to the W-bus.

I have also made a second design that uses an additional 74LS245 bus transceiver.  This allows you, during simulation in ISIS, to view what data is actually stored in each byte of RAM.

Here is a file that contains the schematics for each design.